1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, the present invention relates to a semiconductor memory device having an input/output architecture which allows for an increase in write and read operation speeds.
A claim of the priority is made to Korean Patent Application No. 2003-8207, filed on Feb. 10, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
In a semiconductor memory device, particularly a dynamic random access memory (DRAM), it is important to maximize the input/output data rate during high-speed write and read operations. To this end, a data prefetch structure is generally adopted in the input/output architecture of the DRAM.
During a read operation, the data prefetch structure is characterized in that multi-bit data is simultaneously read in parallel from a memory core of DRAM at a low speed and is output in series to the outside of the memory at a high speed. During a write operation, data is input in parallel from the outside of the memory at a high speed and the input data is written in series to the memory at a low speed.
As a result, the number of prefetch cells that needs to be accessed in parallel must be increased in order to enhance the operating speed of the DRAM. However, an increase in the number of prefetch cells results in an increase in noise, and the random selection of columns can be restricted. As a result, the efficiency of read/write operations can be reduced.
FIG. 1 is a circuit diagram of a conventional semiconductor memory device having a conventional input/output architecture. FIG. 2 is a timing diagram illustrating a read operation of the semiconductor memory device of FIG. 1.
Referring to FIGS. 1 and 2, a column address decoder 11 decodes a column address ADD that is externally input to the semiconductor memory device and provides the decoded result to a column selection line enable control circuit 12. The column selection line enable control circuit 12 receives the decoded result and generates corresponding column selection line enable signals CSLi, CSLj, . . . , and CSLk, in response to a clock signal CLK.
In response to the column selection line enable signals CSLi, CSLj, . . . , and CSLk, a switching circuit 13 selectively connects pairs of bit lines BLi, BLj, . . . ,BLk to a pair of input/output (I/O) lines IO. The pairs of bit lines BLi, BLj, . . . ,BLk are connected to memory cells MCi, MCj, . . . , MCk in a memory cell array 10, respectively,
During a read operation, an I/O line sense amplification circuit IOSA 14a senses and amplifies data from the pair of I/O lines IO, and outputs the data to a pair of data lines DIO, in response to a clock signal CLK. The data from the pair of data lines DIO is input to an I/O pin DQ via an I/O buffer 16. A precharge circuit 15 precharges the pair of I/O lines IO in response to a falling edge of the clock signal CLK.
During a write operation, a write driver DRV 14b receives data from the pair of data lines DIO input via the I/O buffer 16, and transmits the data to the pair of I/O lines IO, in response to the clock signal CLK. The data from the pair of I/O lines IO is written to the memory cells MCi, MCj, . . . , MCk using the switching circuit 13.
Although not shown in the drawings, a register may be installed around the I/O buffer 16. The register enables a high-speed input/output operation by simultaneously reading multi-bit data in parallel and converting the data format from parallel to series.
In a semiconductor memory device with a conventional I/O structure, a read operation requires development and precharging of the pair of I/O lines IO before the next read operation. In fact, development and precharging of the pair of I/O lines IO must be made within a period of the clock signal CLK. However, the higher the integration of the semiconductor memory device, the more loads that are applied onto the pair of I/O lines 10. Furthermore, as the data input/output operation speed of the semiconductor memory device increases, it becomes more difficult to coordinate the development and precharging of the pair of I/O lines IO within a period of the clock signal CLK. These restrictions limit the ability to increase the write and read operation speeds of a semiconductor memory device having a conventional input/output structure.